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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
Figure 20 – Boundary Scan Architecture  
Boundary Scan  
TDI  
Register  
Device Identification  
Register  
Bypass  
Register  
Instruction  
Register  
and  
Mux  
DFF  
TDO  
Decode  
Control  
TMS  
Test  
Access  
Port  
Select  
Controller  
Tri-state Enable  
TRSTB  
TCK  
The boundary scan architecture consists of a TAP controller, an instruction  
register with instruction decode, a bypass register, a device identification register  
and a boundary scan register. The TAP controller interprets the TMS input and  
generates control signals to load the instruction and data registers. The  
instruction register with instruction decode block is used to select the test to be  
executed and/or the register to be accessed. The bypass register offers a single  
bit delay from primary input, TDI to primary output , TDO. The device  
identification register contains the device identification code.  
The boundary scan register allows testing of board inter-connectivity. The  
boundary scan register consists of a shift register placed in series with device  
inputs and outputs. Using the boundary scan register, all digital inputs can be  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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