PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin/ Enable
TRSTB
Notes:
Register Bit
Cell Type
TAP Input
Device I.D.
-
1. Register bit 364 is the first bit of the scan chain (closest to TDI).
2. Enable cell pinname_OEN, tristates pin pinname when set high.
3. Cells ‘Logic 0’ and ‘Logic 1’ are Input Observation cells whose input pad is
bonded to VSS or VDD internally.
4. Cells titled ‘Unconnected’ are Output or Bi-directional cells whose pad is
unconnected to the device package. In the case of bi-directional cells, the
pad always drives (i.e. never tri-states) and the pad input is the same logic
value as the pad output.
Figure 16 – Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
Input
to internal
Pad
logic
G1
G2
SHIFT-DR
1 2
1 2
1 2
1 2
D
MUX
C
I.D. Code bit
CLOCK-DR
Scan Chain In
In this diagram and those that follow, CLOCK-DR is equal to TCK when the
current controller state is SHIFT-DR or CAPTURE-DR, and unchanging
otherwise. The multiplexor in the center of the diagram selects one of four
inputs, depending on the status of select lines G1 and G2. The ID Code bit is as
listed in the table above.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
311
PMC [ PMC-SIERRA, INC ]
