PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x10 : CBI Memory Base Address Register
Bit
Type
Function
Default
Bit 31
to
R/W
BSAD[27:9]
00000H
Bit 13
Bit 12
R
BSAD[8:0]
000H
to
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
PRFTCH
TYPE[1]
TYPE[0]
MSI
0
0
0
0
The GPIC supports memory mapping only. At boot-up the internal registers
space is mapped to memory space. The device driver can disable memory space
through the PCI Configuration Command register.
MSI:
MSI is forced low to indicate that the internal registers map into memory
space.
TYPE[1:0]:
The TYPE field indicates where the internal registers can be mapped. The
encoding 00B indicates the registers may be located anywhere in the 32 bit
address space, 01B indicates that the registers must be mapped below 1
Meg in memory space, 10B indicates the base register is 64 bits and the
encoding 11B is reserved.
The TYPE field is set to 00B to indicate that the CBI registers can be mapped
anywhere in the 32 bit address space.
PRFTCH:
The Prefetchable (PRFTCH) bit is set if there are no side effects on reads
and data is returned on all the lanes regardless of the byte enables.
Otherwise the bit is cleared. TSBs contain registers, such as interrupt status
registers, in which bits are cleared on a read. If the PCI Host is caching data
there is a possibility an interrupt status could be lost if data is prefetched, but
the cache is flushed and the data is not used. The PRFTCH bit is forced low
to indicate that prefetching of data is not supported for internal registers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
292
PMC [ PMC-SIERRA, INC ]
