PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 40 – Test Mode Register Memory Map
Address TA[12:0]
Register
Normal Mode Registers
0x0000 - 0x07FC
0x0800 - 0x107C
0x1080 - 0x10FC
0x1100 - 0x11FC
0x1200 - 0x123C
0x1240 - 0x127C
0x1280 - 0x12FC
0x1300 - 0x137C
0x1380 - 0x13BC
0x13C0 - 0x13FC
0x1400 - 0x14FC
0x1500 - 0x151C
0x1520 - 0x15BC
0x15C0 - 0x15FC
0x1600 - 0x167C
0x1680 - 0x16FC
0x1700 - 0x17FC
0x1800 - 0x18FC
0x1900 - 0x19FC
0x1A00 - 0x1AFC
0x1B00 - 0x1BFC
0x1C00 - 0x1CFC
0x1D00 - 0x1DFC
0x1E00 - 0x1FFC
Reserved
GPIC Test Registers
RCAS Test Registers
RHDL Test Registers
Reserved
RMAC Test Registers
TMAC Test Registers
THDL Test Registers
Reserved
TCAS Test Registers
PMON Test Registers
Reserved
SBI EXTRACT Test Registers
Reserved
SBI INSERT Test Registers
Reserved
SBI PISO#1 Test Registers
SBI PISO#2 Test Registers
SBI PISO#3 Test Registers
SBI SIPO#1 Test Registers
SBI SIPO#2 Test Registers
SBI SIPO#3 Test Registers
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
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296
PMC [ PMC-SIERRA, INC ]
