RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
RPFEI:
The receive packet format error interrupt status bit (RPFEI) reports receive
packet format error interrupts to the microprocessor. RPFEI is set high upon
receipt of a packet that is longer than the maximum programmed length, of a
packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a
packet that is not octet aligned. RPFEI remains valid when interrupts are
disabled and may be polled to detect receive packet format error events.
RFOVRI:
The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive
FIFO overrun error interrupts to the microprocessor. RFOVRI is set high on
attempts to write data into the logical FIFO of a channel when it is already full.
RFOVRI remains valid when interrupts are disabled and may be polled to
detect receive FIFO overrun events.
TPRTYI:
The transmit parity error interrupt status bit (TPRTYI) reports the detection of
a parity on the transmit APPI. TPRTYI is set high upon detection of a parity
error. TPRTYI remains valid when interrupts are disabled and may be polled
to detect parity errors.
TUNPVI:
The transmit unprovisioned error interrupt status bit (TUNPVI) reports an
attempted data transmission to an unprovisioned channel FIFO. TUNPVI is
set high upon attempts to write data to an unprovisioned channel FIFO.
TUNPVI remains valid when interrupts are disabled and may be polled to
detect an attempt to write data to an unprovisioned channel FIFO.
TFOVRI:
The transmit FIFO overflow error interrupt status bit (TFOVRI) reports
transmit FIFO overflow error interrupts to the microprocessor. TFOVRI is set
high upon attempts to write data to the logical FIFO when it is already full.
TFOVRI remains valid when interrupts are disabled and may be polled to
detect transmit FIFO overflow events. (Note – Transmit FIFO overflows will
not occur if channels are properly polled on the Transmit APPI before
transferring data.)
TFUDRI:
The transmit FIFO underflow error interrupt status bit (TFUDRI) reports
transmit FIFO underflow error interrupts to the microprocessor. TFUDRI is set
PROPRIETARY AND CONFIDENTIAL
75
PMC [ PMC-SIERRA, INC ]
