RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x008 : FREEDM-32A256 Master Interrupt Status
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
R
R
R
R
TFUDRI
TFOVRI
TUNPVI
TPRTYI
Unused
X
X
X
X
XXH
Bit 11
to
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
RFOVRI
RPFEI
RABRTI
RFCSEI
Unused
Unused
X
X
X
X
X
X
This register reports the interrupt status for various events detected or initiated by
the FREEDM-32A256. Reading this registers acknowledges and clears the
interrupts.
RFCSEI:
The receive frame check sequence error interrupt status bit (RFCSEI) reports
receive FCS error interrupts to the microprocessor. RFCSEI is set high when
a mismatch between the received FCS code and the computed CRC residue
is detected. RFCSEI remains valid when interrupts are disabled and may be
polled to detect receive FCS error events.
RABRTI:
The receive abort interrupt status bit (RABRTI) reports receive HDLC abort
interrupts to the microprocessor. RABRTI is set high upon receipt of an abort
code (at least 7 contiguous 1’s). RABRTI remains valid when interrupts are
disabled and may be polled to detect receive abort events.
PROPRIETARY AND CONFIDENTIAL
74
PMC [ PMC-SIERRA, INC ]
