RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
must sample the TRDY output high before continuing to burst data across the Tx
APPI.
A maximum of 256 bytes may be stored in one of the two FIFOs for any given
burst transfer. The first word of each burst transfer contains a prepended
address field. (The maximum length of a burst transfer on the Tx APPI is
therefore 129 words, including prepend.) A separate storage element samples
the 10 least significant bits of the prepended channel address to associate the
data with a specific channel. The 3 most significant bits must match the base
address programmed into the TAPI256 Control register for the TAPI256 to
respond to the data transaction on the Tx APPI.
The writer controller provides a means for writing data from the Tx APPI into the
FIFOs. The writer controller can accept data when there is at least one
completely empty FIFO. When a data transfer begins and there are no empty
FIFOs, the writer controller catches the data provided on the Tx APPI and
throttles the upper layer device. The writer controller will continue to throttle the
upper layer device until at least one FIFO is completely empty and can accept a
maximum burst transfer of data.
The whisper controller provides the channel address of the data being written
into the FIFO. As soon as the first word of data has been written into the FIFO,
the whisper controller provides the channel information for that data to the
downstream THDL256 block. The whisper controller will wait for
acknowledgement and the reader controller is then requested to read the data
from the FIFO. Once the reader controller has commenced the data transfer, the
whisper controller will provide the channel information for the other FIFO. The
whisper controller alternates between the two FIFOs in the order in which data is
written into them.
The reader controller provides a means of reading data out of the FIFOs. When
the writer controller indicates that data has been completely written into one of
the two FIFOs, the reader controller is permitted to read that data. The reader
controller will then wait for a request for data from the THDL256 block. When
requested to transfer data, the reader controller will completely read all the data
out of the FIFO before indicating to the writer controller that more data may be
written into the FIFO. Because the reader controller reads data out of the FIFOs
in the order in which they were filled, the THDL256 block will request data for
channels in the order in which they were whispered. The reader controller
manages the read and write FIFO pointers to allow simultaneous reading and
writing of data to/from the double buffer FIFO.
PROPRIETARY AND CONFIDENTIAL
55
PMC [ PMC-SIERRA, INC ]
