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PM7383-PI 参数 Datasheet PDF下载

PM7383-PI图片预览
型号: PM7383-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
Figure 4 – Partial Packet Buffer Structure  
Partial Packet  
Buffer RAM  
Block  
Pointer RAM  
16 bytes  
16 bytes  
16 bytes  
16 bytes  
XX  
0x03  
XX  
Block 0  
Block 1  
Block 2  
Block 3  
Block 0  
Block 1  
Block 2  
Block 3  
0xC8  
16 bytes  
16 bytes  
0x01  
XX  
Block 200  
Block 200  
Block 2047  
Block 2047  
The partial packet buffer processor is divided into three sections: writer, reader  
and roamer. The writer is a time-sliced state machine which writes the HDLC  
data and status information from the HDLC processor into a channel FIFO in the  
packet buffer RAM. The reader transfers channel FIFO data from the packet  
buffer RAM to the downstream Receive Any-PHY Interface block (RAPI256).  
The roamer is a time-sliced state machine which tracks channel FIFO buffer  
depths and signals the reader to service a particular channel. If a buffer over-run  
occurs, the writer ends the current packet from the HDLC processor in the  
channel FIFO with an overrun flag and ignores the rest of the packet.  
The FIFO algorithm of the partial packet buffer processor is based on a  
programmable per-channel transfer size. Instead of tracking the number of full  
blocks in a channel FIFO, the processor tracks the number of transactions.  
Whenever the partial packet writer fills a transfer-sized number of blocks or writes  
an end-of-packet flag to the channel FIFO, a transaction is created. Whenever  
the partial packet reader transmits a transfer-size number of blocks or an end-of-  
PROPRIETARY AND CONFIDENTIAL  
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