RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
accessed from RAM during a null clock cycle inserted by the TCAS256 block.
Writing new provisioning data to a channel resets the channels entire state
vector.
8.7.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM
which is divided into 16 byte blocks. A block pointer RAM is used to chain the
partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous
sections of RAM can be allocated in the partial packet buffer RAM to create a
channel FIFO. Figure 5 shows an example of three blocks (blocks 1, 3, and 200)
linked together to form a 48 byte channel FIFO. The three pointer values would
be written sequentially using indirect block write accesses. When a channel is
provisioned within this FIFO, the state machine can be initialized to point to any
one of the three blocks.
Figure 5 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
16 bytes
16 bytes
16 bytes
16 bytes
XX
0x03
XX
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
0xC8
16 bytes
16 bytes
0x01
XX
Block 200
Block 200
Block 2047
Block 2047
PROPRIETARY AND CONFIDENTIAL
58
PMC [ PMC-SIERRA, INC ]
