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PM7383-PI 参数 Datasheet PDF下载

PM7383-PI图片预览
型号: PM7383-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
FCS, the minimum packet length is four bytes while those with CRC-32 as FCS,  
the minimum length is six bytes. An HDLC packet is aborted when seven  
contiguous "1" bits (with no inserted "0" bits) are received. At least one flag byte  
must exist between HDLC packets for delineation. Contiguous flag bytes, or all  
ones bytes between packets are used as an "inter-frame time fill". Adjacent flag  
bytes may share zeros.  
Figure 2 – HDLC Frame  
Flag  
Information  
HDLC Packet  
FCS  
Flag  
Flag  
The CRC algorithm for the frame checking sequence (FCS) field is either a  
CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram  
2
n-1  
n
using the generating polynomial g(X) = 1 + g X + g X +…+ g X  
n-1  
+ X . The  
1
2
CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +  
5
12  
16  
X + X + X . The CRC-32 FCS is four bytes in size and has a generating  
2
4
5
7
8
10  
11  
12  
16  
22  
polynomial g(X) = 1 + X + X + X + X + X + X + X + X + X + X + X  
23  
26  
32  
+ X + X + X . The first FCS bit received is the residue of the highest term.  
Figure 3 – CRC Generator  
g
g
g
n-1  
1
2
Message  
D
D
D
D
n-1  
0
1
2
LSB  
Parity Check Digits  
MSB  
8.3 Receive Channel Assigner  
The Receive Channel Assigner block (RCAS256) processes up to 32 serial links.  
Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to  
support T1/J1/E1 channelised traffic or to support unchannelised traffic. When  
configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a  
clock and frame pulse. All links configured for 8.192 Mbps H-MVIP traffic share a  
PROPRIETARY AND CONFIDENTIAL  
45