RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
9. TBD set-up time is measured with a 20 pF load on TBCLK. The set-up time
increases by typically 1 ns for each 10 pF of extra load on TBCLK.
Figure 31 – Receive Data & Frame Pulse Timing (2.048 Mbps H-MVIP Mode)
RMVCK[n]
tS
tH
tS
RFPB
RFPB
RFPB[n]
tH
RD_2MVIP
RD_2MVIP
RD[m]
(m=8n,8n+1...8n+7)
Figure 32 – Receive Data & Frame Pulse Timing (8.192 Mbps H-MVIP Mode)
RMV8FPC
tS
tH
RFP8B
RFP8B
RFP8B
tP
MVC
RMV8DC
tS
tH
RD_8MVIP
RD_8MVIP
RD[n]
PROPRIETARY AND CONFIDENTIAL
208