RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
15
FREEDM-32A256 TIMING CHARACTERISTICS
(T = -40°C to +85°C, VDD3.3 = 3.0 V to 3.6V, VDD2.5 = 2.3 V to 2.7 V)
A
Table 23 – FREEDM-32A256 Link Input (Figure 31 to Figure 34)
Symbol
Description
Min
Max
Units
RCLK[31:0] Frequency (See Note 3)
RCLK[31:0] Frequency (See Note 4)
RCLK[2:0] Frequency (See Note 5)
RCLK[31:3] Frequency (See Note 5)
RCLK[31:0] Duty Cycle
1.542
2.046
1.546
2.050
51.84
10
MHz
MHz
MHz
MHz
%
40
60
RMVCK[3:0] Frequency (See Note 6)
RMVCK[3:0] Duty Cycle
4.092
40
4.100
60
MHz
%
RMV8DC Frequency (See Note 7)
RMV8DC Duty Cycle
RMV8FPC Frequency (See Note 8)
RMV8FPC Duty Cycle
RMV8DC to RMV8FPC skew
SYSCLK Frequency
SYSCLK Duty Cycle
16.368 16.400 MHz
40
4.092
40
-10
25
40
1
60
4.100
60
%
MHz
%
tP
tS
10
ns
MVC
RD
45
60
MHz
%
ns
RD[2:0] Set-Up Time
tH
RD[2:0] Hold Time
2
ns
RD
tS
tH
RD[31:3] Set-Up Time
5
ns
RD
RD[31:3] Hold Time
5
ns
RD
tS
RD[31:0] Set-Up Time
5
ns
RD_2MVIP
(2.048 Mbps H-MVIP Mode)
tH
RD[31:0] Hold Time
5
ns
RD_2MVIP
(2.048 Mbps H-MVIP Mode)
PROPRIETARY AND CONFIDENTIAL
206
PMC [ PMC-SIERRA, INC ]
