RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Symbol
Description
Min
Max
Units
tP
Valid Read to Valid Data
Propagation Delay
40
ns
RD
tZ
tP
Valid Read Deasserted to Output
Tristate
Valid Read Deasserted to INTB High
20
50
ns
ns
RD
INTH
Figure 41 – Microprocessor Read Access Timing
tS
AR
A[11:2]
Valid
Address
tH
AR
tS
ALR
tV
tH
L
ALR
ALE
tH
tS
LR
LR
(CSB+RDB)
INTB
tP
INTH
tZ
tP
RD
RD
Valid Data
D[15:0]
Notes on Microprocessor Read Timing:
1. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
PROPRIETARY AND CONFIDENTIAL
216
PMC [ PMC-SIERRA, INC ]
