RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 42 – Microprocessor Write Access Timing
A[7:0]
Valid Address
tS
tH
ALW
ALW
tV
L
tS
tH
LW
LW
ALE
(CSB+WRB)
D[7:0]
tS
tV
tS
tH
AW
AW
WR
tH
DW
DW
Valid Data
Notes on Microprocessor Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. Microprocessor Interface timing applies to normal mode register accesses only.
3. In non-multiplexed address/data bus architectures, ALE should be held high,
parameters tS
, tH
, tV , tS , and tH
are not applicable.
ALW
ALW
L
LW
LW
4. Parameters tH
and tS
are not applicable if address latching is used.
AW
AW
Table 28 – JTAG Port Interface (Figure 43)
Symbol
Description
Min
Max
Units
TCK Frequency
TCK Duty Cycle
TMS Set-up time to TCK
1
60
MHz
%
ns
40
50
tS
TMS
PROPRIETARY AND CONFIDENTIAL
218
PMC [ PMC-SIERRA, INC ]
