RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 38 – BERT Output Timing
RBCLK
tPRBD
RBD
Table 25 – Any-PHY Packet Interface (Figure 39 to Figure 40)
Symbol
Description
Min
Max
Units
RXCLK Frequency
RXCLK Duty Cycle
TXCLK Frequency
TXCLK Duty Cycle
All APPI Inputs Set-up time to
RXCLK, TXCLK
0
40
0
40
4
50
60
50
60
MHz
%
MHz
%
tS
ns
APPI
tH
All APPI Inputs Hold time to RXCLK, 1
TXCLK
ns
ns
ns
ns
APPI
tP
RXCLK, TXCLK to all APPI Outputs
Valid
2
2
2
12
12
APPI
t
t
RXCLK, TXCLK to APPI Outputs
Tristate
Z
APPI
RXCLK, TXCLK to APPI Outputs
Driven
ZD
APPI
Notes on Any-PHY Packet Interface Output Timing:
1. Maximum and minimum output propagation delays are measured with a 100 pF load
on all the outputs.
PROPRIETARY AND CONFIDENTIAL
213
PMC [ PMC-SIERRA, INC ]
