RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 33 – Receive Data Timing (Non H-MVIP Mode)
RCLK[n]
tSRD
tHRD
RD[n]
Figure 34 – BERT Input Timing
TBCLK
tSTBD
tHTBD
TBD
Table 24 – FREEDM-32A256 Link Output (Figure 35 to Figure 38)
Symbol
Description
Min
Max
Units
TCLK[31:0] Frequency (See Note 4)
TCLK[31:0] Frequency (See Note 5)
TCLK[2:0] Frequency (See Note 6)
TCLK[31:3] Frequency (See Note 6)
TCLK[31:0] Duty Cycle
1.542
2.046
1.546
2.050
51.84
10
MHz
MHz
MHz
MHz
%
40
60
TMVCK[3:0] Frequency (See Note 7)
TMVCK[3:0] Duty Cycle
4.092
40
4.100
60
MHz
%
TMV8DC Frequency (See Note 8)
TMV8DC Duty Cycle
16.368 16.400 MHz
40
60
%
TMV8FPC Frequency (See Note 9)
4.092
4.100
MHz
PROPRIETARY AND CONFIDENTIAL
209
PMC [ PMC-SIERRA, INC ]
