RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
10
TEST FEATURES DESCRIPTION
The FREEDM-32A256 also supports a standard IEEE 1149.1 five signal JTAG
boundary scan test port for use in board testing. All device inputs may be read
and all device outputs may be forced via the JTAG test port.
10.1 Test Mode Registers
Test mode registers are used to apply test vectors during production testing of
the FREEDM-32A256. Production testing is enabled by asserting the PMCTEST
pin. During production tests, FREEDM-32A256 registers are selected by the
TA[12:0] pins. The address of a register on TA[12:0] is identical to the offset of
that register when production testing is disabled (PMCTEST low). Read
accesses are enabled by asserting TRDB low while write accesses are enabled
by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0]
pins. Test mode registers (as opposed to normal mode registers) are selected
when TA[12]/TRS is set high.
PROPRIETARY AND CONFIDENTIAL
159
PMC [ PMC-SIERRA, INC ]
