RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
register before triggering the write. LEVEL[3:0] reflects the value written until
the completion of a subsequent indirect channel read operation.
The HDLC processor starts transmitting a packet when the channel FIFO free
space is less than or equal to the level specified in the appropriate Start
Transmission Level column of the following table or when an end of a packet
is stored in the channel FIFO. When the channel FIFO free space is greater
than or equal to the level specified in the Starving Trigger Level column of the
following table and the HDLC processor is transmitting a packet and an end of
a packet is not stored in the channel FIFO, the partial packet buffer makes
expedited requests to the TAPI256 to retrieve XFER[3:0] + 1 blocks of data.
To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to
be less than or equal to the start transmission level set by LEVEL[3:0] and
TRANS. Alternatively, the channel transfer size can be set such that the total
number of blocks in the logical channel FIFO, minus the start transmission
level, is an integer multiple of the channel transfer size. The starving trigger
level must always be set to a number of blocks greater than or equal to the
channel transfer size.
IDLE:
The interframe time fill bit (IDLE) configures the HDLC processor to use flag
bytes or HDLC idle as the interframe time fill between HDLC packets. The
value of IDLE to be written to the channel provision RAM, in an indirect
channel write operation, must be set up in this register before triggering the
write. When IDLE is set low, the HDLC processor uses flag bytes as the
interframe time fill. When IDLE is set high, the HDLC processor uses HDLC
idle (all one’s bit with no bit-stuffing pattern is transmitted) as the interframe
time fill. IDLE reflects the value written until the completion of a subsequent
indirect channel read operation.
TRANS:
The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0]
bits, configure the various channel FIFO free space levels which trigger the
HDLC processor to start transmission of a HDLC packet as well as trigger the
partial packet buffer to request data from the TAPI256 as shown in the
following table. The transmission start mode to be written to the channel
provision RAM, in an indirect write operation, must be set up in this register
before triggering the write. TRANS reflects the value written until the
completion of a subsequent indirect channel read operation.
PROPRIETARY AND CONFIDENTIAL
126
PMC [ PMC-SIERRA, INC ]
