RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x388 : THDL Indirect Channel Data #2
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
7BIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
INVERT
DFCS
Reserved
FLEN[10]
FLEN[9]
FLEN[8]
FLEN[7]
FLEN[6]
FLEN[5]
FLEN[4]
FLEN[3]
FLEN[2]
FLEN[1]
FLEN[0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains data to be inserted into the channel provision RAM in an
indirect write operation.
FLEN[10:0]:
The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that
is provisioned to the circular channel FIFO specified by the FPTR[10:0] block
pointer. The FIFO length to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before
triggering the write.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
32A256 device.
PROPRIETARY AND CONFIDENTIAL
122
PMC [ PMC-SIERRA, INC ]
