RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x38C : THDL Indirect Channel Data #3
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
TRANS
IDLE
0
0
X
X
0
0
0
0
0
0
0
X
0
0
0
0
Unused
Unused
LEVEL[3]
LEVEL[2]
LEVEL[1]
LEVEL[0]
FLAG[2]
FLAG[1]
FLAG[0]
Unused
XFER[3]
XFER[2]
XFER[1]
XFER[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 4
Bit 3
Bit 2
Bit 1
R/W
R/W
R/W
R/W
Bit 0
This register contains data read from the channel provision RAM after an indirect
read operation or data to be inserted into the channel provision RAM in an
indirect write operation.
XFER[3:0]:
The indirect channel transfer size (XFER[3:0]) specifies the amount of data
the partial packet processor requests from the TAPI256 block. The channel
transfer size to be written to the channel provision RAM, in an indirect write
operation, must be set up in this register before triggering the write. When
the channel FIFO free space reaches or exceeds the limit specified by
XFER[3:0], the partial packet processor will inform the TAPI256 so that a poll
on that channel reflects that the channel FIFO is able to accept XFER[3:0] + 1
blocks of data. FIFO free space and transfer size are measured in number of
PROPRIETARY AND CONFIDENTIAL
124
PMC [ PMC-SIERRA, INC ]
