RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Table 9 – Transmit Descriptor Fields
Field
Description
Data Buffer Start
Address [31:0]
The Data Buffer Start Address[31:0] bits point to the
data buffer in host memory.
The Data Buffer Start Address field is valid in all TDs
Bytes In Buffer [15:0]
P
The Bytes In Buffer[15:0] field is used by the host to
indicate the total number of bytes to be transmitted in
the current TD. Zero length buffers are illegal.
The Priority bit is set by the host to indicate the
priority of the associated packet in a two level quality
of service scheme. Packets with its P bit set high are
queued in the high priority queue in the TMAC672.
Packets with the P bit set low are queued in the low
priority queue. Packets in the low priority queue will
not begin transmission until the high priority queue is
empty.
ABT
IOC
The Abort (ABT) bit is used by the host to abort the
transmission of a packet. When ABT is set to logic 1,
the packet will be aborted after all the data in the
buffer has been transmitted. If ABT is set to logic 1 in
the current TD, the M bit must be set low and the CE
bit must be set to high.
The Interrupt On Complete (IOC) bit is used by the
host to instruct the TMAC672 to interrupt the host
when the current TD's data buffer has been read.
When IOC is logic 1, the TMAC672 asserts the IOCI
interrupt when the data buffer has been read.
Additionally, the Free Queue FIFO will be flushed. If
IOC is logic zero, the TMAC672 will not generate an
interrupt and the Free Queue FIFO will operate
normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
