RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 40 – PCI Fast Back to Back
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
T
T
Data
Byte En
Data
Data
Byte Enable
AD[31:0]
Address
Address
Bus Cmd
Bus Cmd
T
C/BEB[3:0]
IRDYB
T
T
TRDYB
DEVSELB
14.6 BERT Interface
The timing relationship between the receive link clock and data (RCLK[n] /
RD[n]) and the receive BERT port signals (RBCLK / RBD) is shown in Figure 41.
BERT is not supported for H-MVIP links. For non H-MVIP links, the selected
RCLK[n] is placed on RBCLK after an asynchronous delay. The selected receive
link data (RD[n]) is sampled on the rising edge of the associated RCLK[n] and
transferred to RBD on the falling edge of RBCLK.
Figure 41 – Receive BERT Port Timing
RCLK[n]
B1 B2 B3 B4 X B5 X
X
X B6 B7 B8 B1 X
RD[n]
RBCLK
B1 B2 B3 B4
B5
B6 B7 B8 B1
RBD
The timing relationship between the transmit link clock and data (TCLK[n] /
TD[n]) and the transmit BERT port signals (TBCLK / TBD) is shown in Figure 42.
BERT is not supported for H-MVIP links. TCLK[n] is shown to have an arbitrary
gapping. When TCLK[n] is quiescent, TBD is ignored (X in Figure 42). The
selected TCLK[n] is buffered and placed on TBCLK. The transmit BERT data
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
303
PMC [ PMC-SIERRA, INC ]
