RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x10C : RCAS Channel Disable
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
R/W
CHDIS
0
Bit 14
Unused
XXH
to
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DCHAN[9]
DCHAN[8]
DCHAN[7]
DCHAN[6]
DCHAN[5]
DCHAN[4]
DCHAN[3]
DCHAN[2]
DCHAN[1]
DCHAN[0]
0
0
0
0
0
0
0
0
0
0
This register controls the disabling of one specific channel to allow orderly
provisioning of time-slots associated with that channel.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
DCHAN[9:0]:
The disable channel number bits (DCHAN[9:0]) selects the channel to be
disabled. When CHDIS is set high, the channel specified by DCHAN[9:0] is
disabled. Data in time-slots associated with the specified channel is ignored.
When CHDIS is set low, the channel specified by DCHAN[9:0] operates
normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
127
PMC [ PMC-SIERRA, INC ]
