RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x18C – 0x1FC : RCAS Links #3 to #31 Configuration
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXXXH
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
MODE[2]
MODE[1]
MODE[0]
0
0
0
This register configures operational modes of receive links #3 to #31.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding receive link.
Table 17 details this procedure. When link 4m (0?m?7) is configured for
operation in 8.192 Mbps H-MVIP mode (MODE[2:0]=”111”), data cannot be
received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and
4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation
of the RCAS672. From a channel assignment point of view in the RCAS672
(Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are
treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the
H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64
through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link
4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time-
slots 0 through 31 of link 4m+3.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
131
PMC [ PMC-SIERRA, INC ]
