欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7380 参数 Datasheet PDF下载

PM7380图片预览
型号: PM7380
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380的Datasheet PDF文件第21页浏览型号PM7380的Datasheet PDF文件第22页浏览型号PM7380的Datasheet PDF文件第23页浏览型号PM7380的Datasheet PDF文件第24页浏览型号PM7380的Datasheet PDF文件第26页浏览型号PM7380的Datasheet PDF文件第27页浏览型号PM7380的Datasheet PDF文件第28页浏览型号PM7380的Datasheet PDF文件第29页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
Pin Name  
Type  
Input  
Pin  
No.  
Function  
RD[0]  
N20  
N22  
M21  
L22  
L23  
K21  
J21  
The receive data signals (RD[31:0]) contain  
the recovered line data for the 32  
independently timed links in normal mode  
(PMCTEST set low). Processing of the  
receive links is on a priority basis, in  
descending order from RD[0] to RD[31].  
Therefore, the highest rate link should be  
connected to RD[0] and the lowest to  
RD[31].  
For H-MVIP links, RD[n] contains 32/128  
time-slots, depending on the H-MVIP data  
rate configured (2.048 or 8.192 Mbps).  
When configured for 2.048 Mbps H-MVIP  
operation, RD[31:24], RD[23:16], RD[15:8]  
and RD[7:0] are sampled on every 2nd rising  
edge of RMVCK[3], RMVCK[2], RMVCK[1]  
and RMVCK[0] respectively (at the ¾ point  
of the bit interval). When configured for  
8.192 Mbps H-MVIP operation, RD[4m]  
(0?m?7) are sampled on every 2nd rising  
edge of RMV8DC (at the ¾ point of the bit  
interval).  
For channelised links, RD[n] contains the 24  
(T1/J1) or 31 (E1) time-slots that comprise  
the channelised link. RCLK[n] must be  
gapped during the T1/J1 framing bit position  
or the E1 frame alignment signal (time-slot  
0). The FREEDM-32P672 uses the location  
of the gap to determine the channel  
alignment on RD[n]. RD[31:0] are sampled  
on the rising edge of the corresponding  
RCLK[31:0].  
RD[1]  
RD[2]  
RD[3]  
RD[4]  
RD[5]  
RD[6]  
RD[7]  
J20  
RD[8]  
H23  
G22  
G23  
F23  
E23  
D22  
E20  
C23  
A22  
D20  
B21  
D19  
B20  
A19  
A18  
A17  
A16  
C16  
D15  
C15  
B14  
D13  
B13  
C12  
RD[9]  
RD[10]  
RD[11]  
RD[12]  
RD[13]  
RD[14]  
RD[15]  
RD[16]  
RD[17]  
RD[18]  
RD[19]  
RD[20]  
RD[21]  
RD[22]  
RD[23]  
RD[24]  
RD[25]  
RD[26]  
RD[27]  
RD[28]  
RD[29]  
RD[30]  
RD[31]  
For unchannelised links, RD[n] contains the  
HDLC packet data. For certain transmission  
formats, RD[n] may contain place holder bits  
or time-slots. RCLK[n] must be externally  
gapped during the place holder positions in  
the RD[n] stream. The FREEDM-32P672  
supports a maximum data rate of 10 Mbit/s  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
14  
 复制成功!