RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Pin Name
Type
Input
Pin
No.
Function
TCLK[0]
W21
The transmit line clock signals (TCLK[31:0])
contain the transmit clocks for the 32
independently timed links. Processing of
the transmit links is on a priority basis, in
descending order from TCLK[0] to
TCLK[31]. Therefore, the highest rate link
should be connected to TCLK[0] and the
lowest to TCLK[31].
For channelised T1/J1 or E1 links, TCLK[n]
must be gapped during the framing bit (for
T1/J1 interfaces) or during time-slot 0 (for
E1 interfaces) of the TD[n] stream. The
FREEDM-32P672 uses the gapping
information to determine the time-slot
alignment in the transmit stream.
For unchannelised links, TCLK[n] must be
externally gapped during the bits or time-
slots that are not part of the transmission
format payload (i.e. not part of the HDLC
packet).
TCLK[2:0] is nominally a 50% duty cycle
clock between 0 and 51.84 MHz.
TCLK[31:3] is nominally a 50% duty cycle
clock between 0 and 10 MHz. Typical
values for TCLK[31:0] include 1.544 MHz
(for T1/J1 links) and 2.048 MHz (for E1
links).
TCLK[1]
Y23
TCLK[2]
Y21
TCLK[3]
AA23
AB22
AC23
AA21
AB21
AB20
AC19
AC18
AC17
AB17
AC16
AA16
Y15
TCLK[4]
TCLK[5]
TCLK[6]
TCLK[7]
TCLK[8]
TCLK[9]
TCLK[10]
TCLK[11]
TCLK[12]
TCLK[13]
TCLK[14]
TCLK[15]
TCLK[16]
TCLK[17]
TCLK[18]
TCLK[19]
TCLK[20]
TCLK[21]
TCLK[22]
TCLK[23]
TCLK[24]
TCLK[25]
TCLK[26]
TCLK[27]
TCLK[28]
TCLK[29]
TCLK[30]
TCLK[31]
AB14
Y13
AA13
AB12
AA11
AC11
AA10
AC10
AC9
AB8
AA7
Y7
AB6
The TCLK[n] inputs are invalid and should
be tied low when their associated link is
configured for operation in H-MVIP mode.
AA6
AA5
AC4
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PMC [ PMC-SIERRA, INC ]
