RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
optionally separated by two flags (an opening flag and a closing flag) or a single
flag (combined opening and closing flag). Zeros between flags are not shared.
PCI bus latency may cause one or more channels to underflow, in which case,
the packets are aborted, and the host is notified. For normal traffic, an abort
sequence is generated, followed by inter-frame time fill characters (flags or all-
ones bytes) until a new packet is sourced from the PCI host. No attempt is made
to automatically re-transmit an aborted packet.
Alternatively, in the transmit direction, the FREEDM-32P672 supports a
transparent operating mode. For each provisioned transparent channel, the
FREEDM-32P672 directly inserts the transmitted octets from host memory. If the
transparent channel is assigned to a channelised link, then the octets are aligned
to the transmitted time-slots. If a channel underflows due to excessive PCI bus
latency, an abort sequence is generated, followed by inter-frame time fill
characters (flags or all-ones bytes) to indicate idle channel. Data resumes
immediately when the FREEDM-32P672 receives new data from the host.
The FREEDM-32P672 is configured, controlled and monitored using the PCI bus
interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P672 is
implemented in low power 2.5 Volt 0.25 ꢁm CMOS technology. All non-PCI
FREEDM-32P672 I/O pins are 5 volt tolerant. The FREEDM-32P672 is
packaged in a 329 pin plastic ball grid array (PBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC [ PMC-SIERRA, INC ]
