RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Figure 41 – BERT Output Timing
RBCLK
tPRBD
RBD
Table 36 – PCI Interface (Figure 42)
Symbol
Description
Min
Max
Units
PCICLK Frequency
PCICLK Duty Cycle
33
60
MHz
%
40
7
tS
All PCI Input and Bi-directional Set-up time
to PCICLK
ns
PCI
tH
All PCI Input and Bi-directional Hold time to
PCICLK
0
2
ns
PCI
t
t
t
P
PCICLK to all PCI Outputs Valid
All PCI Output PCICLK to Tri-state
11
28
ns
ns
ns
PCI
Z
PCI
ZN
PCI
All PCI Output Tri-state from PCICLK to
active
2
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
266
PMC [ PMC-SIERRA, INC ]
