RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Figure 38 – Receive Link Input Timing
RCLK[n]
tSRD
tHRD
RD[n]
Figure 39 – BERT Input Timing
TBCLK
tSTBD
tHTBD
TBD
Table 35 – FREEDM-8 Link Output (Figure 40, Figure 41)
Symbol
Description
Min
Max
Units
TCLK[7:0] Frequency (See Note 4)
TCLK[7:0] Frequency (See Note 5)
TCLK[2:0] Frequency (See Note 6)
TCLK[7:3] Frequency (See Note 6)
TCLK[7:0] Duty Cycle
1.542
2.046
1.546
2.05
52
MHz
MHz
MHz
MHz
%
10
40
3
60
t
P
t
P
t
P
TCLK[2:0] Low to TD[2:0] Valid
15
ns
TD
TCLK[7:3] Low to TD[7:3] Valid
RBCLK Low to RBD Valid
5
27
5
ns
ns
TD
-5
RBD
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
264
PMC [ PMC-SIERRA, INC ]
