RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Table 27 – Test Mode Register Memory Map
Address TA[10:0]
Register
0x000 - 0x7FC
0x800 - 0x83C
0x840 - 0x87C
0x880 - 0x8FC
0x900 - 0x9FC
0xA00 - 0xA3C
0xA40 - 0xA7C
0xA80 - 0xAFC
0xB00 - 0xB7C
0xB80 - 0xBBC
0xBC0 - 0xBFF
0xC00 - 0xCFC
0xD00 - 0xD1C
0xD20 - 0xFFF
Normal Mode Registers
Reserved
GPIC Test Registers
Reserved
RCAS Test Registers
RHDL Test Registers
Reserved
RMAC Test Registers
TMAC Test Registers
THDL Test Registers
Reserved
TCAS Test Registers
PMON Test Registers
Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software
compatibility with future, feature-enhanced versions of the product, unused register bits must
be written with logic zero. Reading back unused bits can produce either a logic one or a logic
zero; hence unused register bits should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
12.2 JTAG Test Port
The FREEDM-8 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP
registers: instruction, bypass, device identification and boundary scan. Using the TAP, device
input logic levels can be read, device outputs can be forced, the device can be identified and the
device scan path can be bypassed. For more details on the JTAG port, please refer to the
Operations section.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
227
PMC [ PMC-SIERRA, INC ]
