RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
12
TEST FEATURES DESCRIPTION
The FREEDM-8 also supports a standard IEEE 1149.1 five signal JTAG boundary scan test port
for use in board testing. All device inputs may be read and all device outputs may be forced via
the JTAG test port.
12.1 Test Mode Registers
Test mode registers are used to apply test vectors during production testing of the FREEDM.
Production testing is enabled by asserting the PMCTEST pin. During production tests, FREEDM-
8 registers are selected by the TA[11:0] pins. The address of a register on TA[11:0] is identical to
the PCI offset of that register when production testing is disabled (PMCTEST low). Read
accesses are enabled by asserting TRDB low while write accesses are enabled by asserting
TWRB low. Test mode register data is conveyed on the TDAT[15:0] pins. Test mode registers (as
opposed to normal mode registers) are selected when TA[11]/TRS is set high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
226
PMC [ PMC-SIERRA, INC ]
