RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
(combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may
cause one or more channels to underflow, in which case, the packets are aborted, and the host is
notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill
characters (flags or all-ones bytes) until a new packet is sourced from the PCI host. No attempt is
made to automatically re-transmit an aborted packet.
Alternatively, in the transmit direction, the FREEDM-8 supports a transparent operating mode. For
each provisioned transparent channel, the FREEDM-8 directly inserts the transmitted octets from
host memory. If the transparent channel is assigned to a channelised link, then the octets are
aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency,
an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones
bytes) to indicate idle channel. Data resumes immediately when the FREEDM-8 receives new
data from the host.
The FREEDM-8 is configured, controlled and monitored using the PCI bus interface. The
FREEDM-8 is implemented in low power CMOS technology, with TTL compatible inputs and
outputs. The FREEDM-8 is available in two package options; a 256 pin enhanced ball grid array
(SBGA) package, or a 272 pin plastic ball grid array (PBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
8
PMC [ PMC-SIERRA, INC ]
