RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
6
DESCRIPTION
The PM7366 FREEDM-8 Frame Engine and Datalink Manager device is a monolithic integrated
circuit that implements HDLC processing, and PCI Bus memory management functions for a
maximum of 128 bi-directional channels.
For channelised links, the FREEDM-8 allows up to 128 bi-directional HDLC channels to be
assigned to individual time-slots within a maximum of 8 independently timed T1 or E1 links. The
channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24
concatenated time-slots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots
assigned to any particular channel need not be contiguous within the T1 or E1 link.
For unchannelised links, the FREEDM-8 processes up to 8 bi-directional HDLC channels within 8
independently timed links. The links can be of arbitrary frame format. When limited to two
unchannelised links, each link can be rated at up to 52 MHz when SYSCLK is at 33 MHz. For
lower rate unchannelised links, the FREEDM-8 processes up to 8 links, where the aggregate
clock rate of all the links is limited to 64 MHz, links 0 to 2 can have a clock rate of up to 52 MHz
when SYSCLK is at 33 MHz and links 3 to 7 can have a clock rate of up to 10 MHz. The
FREEDM-8 also supports mixing of up to 8 channelised and unchannelised links. The total
number of channels in each direction is limited to 128. The aggregate clock rate over all 8
possible links is limited to 64 MHz.
In the receive direction, the FREEDM-8 performs channel assignment and packet extraction and
validation. For each provisioned HDLC channel, the FREEDM-8 delineates the packet boundaries
using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags,
as well as, sharing of zeros between flags are supported. The resulting packet data is placed into
the internal 8 kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for
each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus
and into host packet memory. The FREEDM-8 validates the frame check sequence for each
packet, and verifies that the packet is an integral number of octets in length and is within a
programmable minimum and maximum length. The receive packet status is updated before
linking the packet into a receive ready queue. The FREEDM-8 alerts the PCI Host that there are
packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus.
Alternatively, in the receive direction, the FREEDM-8 supports a transparent operating mode. For
each provisioned transparent channel, the FREEDM-8 directly transfers the received octets into
host memory verbatim. If the transparent channel is assigned to a channelised link, then the
octets are aligned to the received time-slots.
In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue.
For each provisioned HDLC channel, the FREEDM-8 DMA's partial packets across the PCI bus
and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by
the FREEDM-8 and frame check sequence is optionally calculated and inserted at the end of each
packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is
automatically inserted when there is no packet data for a particular channel. Sequential packets
are optionally separated by two flags (an opening flag and a closing flag) or a single flag
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
7
PMC [ PMC-SIERRA, INC ]
