RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Pin Name
Type
Pin No.
Function
-PI
-BI
RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
Input
H3
G2
F1
G4
E1
E3
E4
D5
G19
G18
F19
E20
F17
D20
E17
C17
The receive data signals (RD[7:0]) contain the
recovered line data for the 8 independently timed
links. Processing of the receive links is on a priority
basis, in descending order form RD[0] to RD[7].
Therefore, the highest rate link should be connected
to RD[0] and the lowest to RD[7].
For channelised links, RD[n] contains the 24 (T1) or
31 (E1) time-slots that comprise the channelised link.
RCLK[n] must be gapped during the T1 framing bit
position or the E1 frame alignment signal (time-slot
0). The FREEDM-8 uses the location of the gap to
determine the channel alignment on RD[n].
For unchannelised links, RD[n] contains the HDLC
packet data. For certain transmission formats, RD[n]
may contain place holder bits or time-slots. RCLK[n]
must be externally gapped during the place holder
positions in the RD[n] stream. The FREEDM-8
supports a maximum data rate of 10 Mbit/s on an
individual RD[7:3] link and a maximum data rate of 52
Mbit/s on RD[2:0].
RD[7:0] is sampled on the rising edge of the
corresponding RCLK[7:0] clock.
RBD
Tristate
Output
H1
H2
H18
G20
The receive BERT data signal (RBD) contains the
receive bit error rate test data. RBD reports the data
on the selected one of the receive data signals
(RD[7:0]) and is updated on the falling edge of
RBCLK. RBD may be tri-stated by setting the RBEN
bit in the FREEDM-8 Master BERT Control register
low.
RBCLK
Tristate
Output
The receive BERT clock signal (RBCLK) contains the
receive bit error rate test clock. RBCLK is a buffered
version of the selected one of the receive clock
signals (RCLK[7:0]). RBCLK may be tri-stated by
setting the RBEN bit in the FREEDM-8 Master BERT
Control register low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
PMC [ PMC-SIERRA, INC ]
