RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x294 : RMAC Queue Base MSW
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RQB[31]
RQB[30]
RQB[29]
RQB[28]
RQB[27]
RQB[26]
RQB[25]
RQB[24]
RQB[23]
RQB[22]
RQB[21]
RQB[20]
RQB[19]
RQB[18]
RQB[17]
RQB[16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the more significant word of the Receive Queue Base address. The
contents of the companion RMAC Receive Queue Base LSW register is held in a holding register
until a write access to this register, at which point, the base address of the receive queue is
updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
RQB[31:0]:
The receive queue base bits (RQB[31:0]) provides the base address of the Large Buffer
RPDR Free, Small Buffer RPDR Free and RPDR Ready queues in PCI host memory. This
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
140