RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x288 : RMAC Packet Descriptor Table Base LSW
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RPDTB[15]
RPDTB[14]
RPDTB[13]
RPDTB[12]
RPDTB[11]
RPDTB[10]
RPDTB[9]
RPDTB[8]
RPDTB[7]
RPDTB[6]
RPDTB[5]
RPDTB[4]
RPDTB[3]
RPDTB[2]
RPDTB[1]
RPDTB[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the less significant word of the Receive Descriptor Table Base address.
The contents of this register is held in a holding register until a write access to the companion
RMAC Receive Descriptor Table Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
136