RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x007: Clock Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
ROOLE
ROOLV
REFCLKA
RCLKA
TCLKA
X
X
X
0
X
X
X
X
R/W
R
R
R
R
This register provides activity monitoring of the S/UNI-VORTEX clocks. When a
monitored clock signal makes a low to high transition, the corresponding register
bit is set high. The bit will remain high until this register is read, at which point,
all the bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read at periodic
intervals to detect clock failures.
The register also reports the state of the clock synthesis unit that generates the
internal clocks.
TCLKA:
The TCLK active (TCLKA) bit monitors for low to high transitions on the TCLK
transmit FIFO clock input. TCLKA is set high on a rising edge of TCLK, and
is set low when this register is read.
RCLKA:
The RCLK active (RCLKA) bit monitors for low to high transitions on the
RCLK receive FIFO clock input. RCLKA is set high on a rising edge of RCLK,
and is set low when this register is read.
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transitions on the
REFCLK reference clock input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
65
PMC [ PMC-SIERRA, INC ]
