RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x00A: Downstream Cell Interface Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
X
X
X
X
X
0
R/W
R/W
R/W
Reserved
CELLXFERRE
PARERRE
0
0
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for these enables to take effect.
CELLXFERRE:
The Cell Transfer Error Interrupt Enable (CELLXFERRE) register bit is the
interrupt enable for invalid start of cell. When a start of cell occurs when not
expected, INTB is asserted low if this bit is set to logic 1. No external
interrupt is generated if this bit is set to zero (Even if the interrupt is not
enabled, it is always reported in the Downstream Cell Interface Interrupt
Status register).
PARERRE:
The Parity Error Interrupt Enable (PARRERRE) register bit is the interrupt
enable for invalid parity over the TDAT[15:0] data bus. When a parity error
occurs over the TDAT[15:0] data bus, an external interrupt is generated if this
bit is set to one. No external interrupt is generated if this bit is set to zero
(Even if the interrupt is not enabled, it is always reported in the Downstream
Cell Interface Interrupt Status register).
Reserved:
This bit must be logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PMC [ PMC-SIERRA, INC ]
