RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Ball
Ball
Type No. Function
Name
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Input K23 The transmit cell data bus (TDAT[15:0]) carries the
L20 ATM cell octets that are transferred to the internal cell
L22 buffer.
L23
The TDAT[15:0] bus is sampled on the rising edge of
M22
TCLK and is considered valid only when the TENB
M21
signal is asserted low or the TSX signal is asserted
N23
high.
N22
N21
N20
P23
P22
P21
R23
P20
R22
TPRTY
Input T22 The transmit parity (TPRTY) signal completes the
parity (programmable for odd or even parity) of the
TDAT[15:0] bus.
A parity error is indicated by a status bit and a
maskable interrupt.
The TPRTY signal is sampled on the rising edge of
TCLK and is considered valid only when the TENB
signal is asserted or the TSX signal is asserted high.
Microprocessor Bus
CSB
RDB
Input AA17 The active-low chip select (CSB) signal is low during
S/UNI-VORTEX register accesses.
If CSB is not required (i.e., registers accesses are
controlled using the RDB and WRB signals only), CSB
must be connected to an inverted version of the RSTB
input.
Input Y16 The active-low read enable (RDB) signal is low during
S/UNI-VORTEX register read accesses. The S/UNI-
VORTEX drives the D[7:0] bus with the contents of
the addressed register while RDB and CSB are low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
22
PMC [ PMC-SIERRA, INC ]
