RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Ball
Ball
Type No. Function
Name
Downstream (Transmit) Bus
TCLK
Input R21 The transmit FIFO clock (TCLK) is used to transfer
cells from a traffic scheduler device to the internal
downstream cell buffers. TCLK must cycle at a 52
MHz or lower instantaneous rate. TSX, TENB,
TADR[11:0], TPRTY and TDAT[15:0] are sampled on
the rising edge of TCLK. TPA is updated on the rising
edge of TCLK.
TPA
Output U23 The S/UNI-VORTEX indicates the availability of space
in the FIFO associated with a logical channel when
polled using the TADR[11:0] signals. The S/UNI-
VORTEX will drive the TPA signal to the appropriate
value during the second clock cycle following that in
which a particular logical channel is addressed. When
high, TPA indicates that the corresponding buffer
segment is empty and a complete cell may be written.
The buffer status for the particular logical channel
involved in the transfer is updated immediately upon
sampling the first word of the cell when the
INADDUDF bit of the Downstream Cell Interface
Configuration register is logic 0. When the
INADDUDF bit is logic 1, the buffer status is stale until
nine cycles after the cell transfer is completed;
therefore, the master should refrain from polling that
logical channel in the interim.
TPA becomes high impedance when an address not
matching the address space set by the Control
Channel Base Address, Logical Channel Base
Address and Logical Channel Address Range /
Logical Channel Base Address MSB registers is
sampled from the TADR[11:3] inputs.
TPA is updated on the rising edge of TCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
20
PMC [ PMC-SIERRA, INC ]
