RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
will indicate which link is currently chosen as active. This reflected ACTIVE bit
may not have a direct affect on the far end S/UNI-VORTEX or S/UNI-DUPLEX,
but its status is typically debounced (must remain the same for 3 received cells)
and then stored by the far end device. The reflected status is normally
monitored by the control system to determine when protection switching has
been completed. The S/UNI-DUPLEX stores its LVDS active indication in the
ACTIVE bit in Master Configuration register (0x01).
The S/UNI-DUPLEX can override active link selection in the receive direction or
force link selection in the transmit direction (this applies to the S/UNI-DUPLEX to
S/UNI-DUPLEX type configuration) using the Master Configuration register
(0x01). If the S/UNI-DUPLEX is forcing its ACTIVE link status (Master
Configuration register 0x01, RXAUTOSEL = 0) the active receive link and the
transmitted ACTIVE bit on the two LVDS links will reflect the status of the Master
Configuration register ACTIVE bit. If ACTIVE is 0 then LVDS link 1 receiver will
be active and link 1 transmitter will indicate it is active, while LVDS link 2
transmitter will indicate it is inactive. If the ACTIVE bit is 0 the opposite
indications will occur.
9.4 Cell Buffering and Flow Control
The possibility of congestion is inherent in an access multiplexer. In the
downstream direction, the WAN link can generate a burst of cells for a particular
PHY device at a rate far exceeding the modem’s bandwidth capacity. Therefore,
feedback to the core card is required to cause it to buffer and smooth cell bursts
to prevent downstream buffer overflow. In the upstream direction, the subscribed
aggregate bandwidth can exceed that accommodated by the WAN uplink. Flow
control is required to ensure fair access to the uplink, to minimize cell loss and to
minimize the impact of greedy users on others.
9.4.1 LVDS Receive Traffic Flow Control
In the LVDS receive direction the primary task of the S/UNI-DUPLEX is to accept
cells from the active high speed link, inspect the PHYID field to determine the
destination of the cell, and then route the cell to the appropriate parallel bus PHY,
clocked serial data interface, or to the microprocessor port. Because the LVDS
link typically supports a much higher transfer bandwidth than the external
devices, rate decoupling and flow control are implemented. Flow control
signaling is implemented using in-band system overhead appended to each cell
sent over the LVDS link (see Table 16).
On the currently active link user cells (those destined to the parallel bus or
clocked serial data interfaces) and inter-processor communication channel cells
(those destined to the microprocessor port) are processed. On the inactive link
only inter-processor communication cells (hereafter called control cells) are
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
71
PMC [ PMC-SIERRA, INC ]
