RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
HCSI:
The HCSI bit is set high when a HCS error is detected. This bit is reset
immediately after a read to this register.
XFERI:
The XFERI bit indicates that a transfer of accumulated counter data has
occurred. A logic 1 in this bit position indicates that the receive cell counter
and error counter holding registers have been updated. This update is
initiated by writing to the associated (i.e. this link only) Receive High-Speed
Serial HCS Error Count register, one of the associated Receive High-Speed
Serial Cell Counter registers or the Load Performance Meters (0x000)
register. This bit is reset immediately after a read to this register.
OCDI:
The OCDI bit is set high when the cell delineation state machine enters or
exits the SYNC state. The current value of the OCD state is available in the
OCDV bit in the associated Receive High-Speed Serial Cell Filtering
Configuration/Status register. The OCDI bit is reset immediately after a read
to this register.
OVR:
The OVR bit is the overrun status of the associated accumulation holding
registers. A logic 1 in this bit position indicates that a previous transfer
(indicated by XFERI being logic 1) has not been acknowledged before the
next accumulation interval has occurred, and that the contents of the receive
cell counter and HCS error counter holding registers have been overwritten.
OVR is set to logic 0 when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
145
PMC [ PMC-SIERRA, INC ]
