RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x47, 0x57:
RXD1, RXD2 High-Speed Serial Cell Counter (MSB)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
RCELL[23]
RCELL[22]
RCELL[21]
RCELL[20]
RCELL[19]
RCELL[18]
RCELL[17]
RCELL[16]
X
X
X
X
X
X
X
X
RCELL[23:0]:
The RCELL[23:0] bits indicate the number of valid cells received during the
last accumulation interval. Cells filtered due to HCS errors or as stuff cells
are not counted. No cells are transferred when the cell delineation state
machine is in either the HUNT or PRESYNC state. Cells lost due to FIFO
overflows are excluded from the count. The counter should be polled at least
every 30 seconds to avoid saturation.
The contents of these registers become valid a maximum of 300 ns after a
transfer is triggered by a write to these registers, the associated Receive
High-Speed Serial HCS Error Count register or the Load Performance Meters
(0x00) register, and remain valid until another transfer is triggered.
The count saturates at all ones.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
148
PMC [ PMC-SIERRA, INC ]
