RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
state machine is in the 'SYNC' state and cells are passed through the receive
FIFO.
Reserved:
This bit must be logic 0 for correct operation.
HCSPASS:
The HCSPASS bit controls the dropping of cells based on the detection of a
HCS error. When HCSPASS is logic 0, cells containing a HCS error are
dropped. When HCSPASS is logic 1, non-stuff cells are passed to the FIFO
interface regardless of errors detected in the HCS. Stuff cells continue to be
dropped and HCS errors continue to be counted by the performance monitor
registers. Additionally, the HCS verification finite state machine never exits
the ‘SYNC’ state, and hence will never lose cell delineation. This bit is
provided for diagnostic purposes only.
Regardless of the programming of this bit, cells are always dropped while the
cell delineation state machine is in the 'HUNT' or 'PRESYNC' states.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
