RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
FIG. 21 SCI-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER
TIMING ..............................................................................................208
FIG. 22 SCI-PHY INTERFACE, OUTPUT BUS MASTER TRANSFER
TIMING ..............................................................................................209
FIG. 23 ANY-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER
TIMING ..............................................................................................210
FIG. 24 CLOCKED SERIAL DATA TRANSMIT INTERFACE ...........................210
FIG. 25 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 1 BIT
GAP ...................................................................................................211
FIG. 26 CLOCKED SERIAL DATA TRANSMIT INTERFACE, 8 BIT GAP ........211
FIG. 27 CLOCKED SERIAL DATA RECEIVE INTERFACE..............................211
FIG. 28: MICROPROCESSOR INTERFACE READ TIMING...........................218
FIG. 29: MICROPROCESSOR INTERFACE WRITE TIMING .........................220
FIG. 30: RSTB TIMING....................................................................................221
FIG. 31: INGRESS SCI-PHY/ANY-PHY INTERFACE TIMING ........................222
FIG. 32: EGRESS SCI-PHY/ANY-PHY INTERFACE TIMING..........................223
FIG. 33: CLOCKED SERIAL DATA INTERFACE .............................................224
FIG. 34: JTAG PORT INTERFACE TIMING.....................................................226
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
