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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
LIST OF FIGURES  
FIG. 1 TYPICAL TARGET APPLICATION............................................................5  
FIG. 2 THREE STAGE MULTIPLEX ARCHITECTURE........................................7  
FIG. 3 CLOCK AND DATA PHY INTERFACE ......................................................8  
FIG. 4 S/UNI-DUPLEX TO S/UNI-DUPLEX APPLICATIONS.............................10  
FIG. 5 S/UNI-DUPLEX TO S/UNI-DUPLEX PROTECTION  
SWITCHING.........................................................................................11  
FIG. 6 EIGHT BIT SCI-PHY/UTOPIA/ANY-PHY CELL FORMAT.......................58  
FIG. 7 SIXTEEN BIT SCI-PHY/UTOPIA/UTOPIA CELL FORMAT.....................59  
FIG. 8 CELL DELINEATION STATE DIAGRAM.................................................61  
FIG. 9 HIGH-SPEED SERIAL LINK DATA STRUCTURE ..................................64  
FIG. 10 DATAPATH LOOPBACK .......................................................................68  
FIG. 11 MICROPROCESSOR CELL FORMAT..................................................81  
FIG. 12 INPUT OBSERVATION CELL (IN_CELL) ...........................................181  
FIG. 13 OUTPUT CELL (OUT_CELL)..............................................................182  
FIG. 14 BIDIRECTIONAL CELL (IO_CELL).....................................................183  
FIG. 15 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ........183  
FIG. 16 BOUNDARY SCAN ARCHITECTURE ................................................199  
FIG. 17 TAP CONTROLLER FINITE STATE MACHINE ..................................201  
FIG. 18 SCI-PHY INTERFACE, INPUT BUS SLAVE TRANSFER  
TIMING ..............................................................................................205  
FIG. 19 SCI-PHY INTERFACE, INPUT BUS MASTER TRANSFER  
TIMING ..............................................................................................206  
FIG. 20 ANY-PHY INTERFACE, INPUT BUS SLAVE TRANSFER  
TIMING ..............................................................................................207  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
vii  
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