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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7348的Datasheet PDF文件第59页浏览型号PM7348的Datasheet PDF文件第60页浏览型号PM7348的Datasheet PDF文件第61页浏览型号PM7348的Datasheet PDF文件第62页浏览型号PM7348的Datasheet PDF文件第64页浏览型号PM7348的Datasheet PDF文件第65页浏览型号PM7348的Datasheet PDF文件第66页浏览型号PM7348的Datasheet PDF文件第67页  
S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Figure 17 Snapshot of DCB Buffers after addition of Link with smaller transport delay  
DCB  
DCB  
DCB  
DCB  
Link 0  
Link 1  
Link 2  
Link3  
Write  
Pointer 3  
36  
32  
28  
24  
20  
16  
12  
8
Write  
Pointer 0  
25  
21  
17  
13  
9
Write  
Pointer 1  
14  
10  
6
Write  
Pointer 2  
5
7
3
Group  
Read  
Pointer  
1
2
4
Adding a link with a larger transport delay requires the DCB buffer depth to be smaller than the  
DCB for the link with the largest delay. If the desired DCB depth for the new link is less than 0,  
this means that the data for the other links has been played out prior to the arrival of data for the  
new link. This is shown in Figure 18. For the new link to be accepted, delay must be added to  
all other links in the group. When delay is added to the other links in the group, the playout of  
ATM cells is halted until enough delay is built up. This causes CDV for the group. Once the  
delay has been added, the DCB for the new link can be aligned with the existing links and  
added to the round robin for playout. Figure 19 shows the case after delay was added to the  
existing links within the group. The adding of delay to a group may be disabled. In this case, the  
new link would be rejected due to a LODS defect meaning that the DCB could not be aligned  
with the group.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
63  
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