S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
UTOPIA Level 2 Multi-Address Slave Mode
In the UTOPIA Level 2 Multi-address Slave mode, the transmit interface of the S/UNI-IMA-4
appears as a 4 port multi-PHY. An 11-bit configuration register TCAEN (only 4 bits are used in
UL2 mode) controls the response to polling the individual channels within this group of 31
ports. Setting high on TCAEN[0] enables addresses 0 through 7 and TCAEN[3] enables
addresses 24 through 30. This is typically used to allow more than one slave device to share the
Transmit Any-PHY/UTOPIA master bus.
Each FIFO will only assert TCA when polled (using TADR) if it is not in the process of
transferring a cell and if there is room in the FIFO for a complete cell. Unlike Any-PHY, in
UTOPIA Mode the virtual PHY port must first be selected prior to the start of the data transfer.
This selection is done using the same address lines that are used for polling in combination with
the TENB pin.
Any-PHY Slave Mode
In the Any-PHY slave mode, the transmit interface of the S/UNI-IMA-4 appears as a multi-PHY
device with 4 ports used for the data path where all ports are identified in the in-band address.
The configuration register TCAEN controls the response to polling the individual channels
within this group of 4 ports. Setting high on TCAEN[0] enables any group of four ports within
the addresses 0 through 7, and TCAEN[3] enables any group of four ports within the addresses
24 through 31. This is typically used to allow more than one slave device to share the Transmit
Any-PHY/UTOPIA master bus.
Conceptually, the Any-PHY protocol can be divided into two processes: polling and cell
transfer.
Polling in the transmit direction is used by the bus master – typically a traffic buffering and
management device – to determine when a buffered data cell can be safely sent to a PHY. The
S/UNI-IMA-4 provides an independent 3-deep cell buffer FIFO for each virtual PHY. In total,
there are 4 FIFOs. This arrangement ensures that there is no head-of-line blocking, while
providing latitude to the master for servicing high data rate ports as well as low data rate ports.
The traffic manager need only poll those virtual PHYs for which it has cells queued. A cell
transfer can be initiated after a polled virtual PHY asserts the TPA output. Each virtual PHY’s
cell buffer availability status (i.e., the status that will be driven onto the TPA output when the
virtual PHY is polled) is deasserted when the first byte of the last cell is written into the buffer.
It is re-asserted only when the FIFO can accept another complete cell.
In Any-PHY mode, polling is performed using the TADR[6:0] bus in conjunction with the
TCSB. Each S/UNI-IMA-4 uses the TADR[2:0] bits to indicate the 4 logical virtual PHY’s (the
other 4 within this range will be unused). The upper bits from the TADR bus, TADR[6:3], are
compared to the configured address to select the device. The remaining address bits from the
traffic manager are decoded externally and are used to drive the TCSB. The address prepend
field in the cell transfer contains the entire 16-bit address. In 8-bit mode, the prepend address is
reduced to 8-bits.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
45
PMC [ PMC-SIERRA, INC ]
