S/UNI®-JET Data Sheet
Released
When enabled for M23 operation, the C-bits are forced to logic one with the exception of the C-
bit Parity ID bit (first C-bit of the first M-subframe), which is forced to toggle every M-frame.
The T3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit
framing errors, M-bit framing errors, invalid X or P-bits, LCV, or all-zeros.
User control of each of the overhead bits in the DS3 frame is provided. Overhead bits may be
inserted on a bit-by-bit basis from a user supplied data stream. An overhead clock (at 526 kHz)
and a DS3 overhead alignment output are provided to allow for control of the user provided
stream.
10.14 E3 Transmitter
The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into
an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible
with the G.751 and G.832 framing formats.
The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream
based on either the G.751 or G.832 formats and an alignment pulse applied to it by the SPLT
block. All overhead and status bits in each frame format can be individually controlled by register
bits or by the transmit overhead stream. While in certain framing format modes, the E3-TRAN
generates various overhead bytes according to the following format or mode.
In G.832 E3 format, the E3-TRAN:
•
•
•
Inserts the BIP-8 byte calculated over the preceding frame.
Inserts the Trail Trace bytes through the Trail Trace Buffer (TTB) block.
Inserts the FERF bit via a register bit or, optionally, when the E3-FRMR declares OOF, or
when the loss of cell delineation (LCD) defect is declared.
•
Inserts the FEBE bit, which is set to logic one when one or more BIP-8 errors are detected by
the receive framer. If there are no BIP-8 errors indicated by the E3-FRMR, the E3-TRAN sets
the FEBE bit to logic zero.
•
•
Inserts the Payload Type bits based on the register value set by the microprocessor.
Inserts the Tributary Unit multiframe indicator bits either via the TOH overhead stream or by
register bit values set by the microprocessor.
•
•
Inserts the Timing Marker bit via a register bit.
Inserts the Network Operator (NR) byte from the TDPR block when the TNETOP bit in the
S/UNI-JET Data Link and FERF Control Register is logic one; otherwise, the NR byte is set
to all ones. The NR byte can be overwritten by using the TOH[x] and TOHINS[x] input pins.
All eight bits of the Network Operator byte are available for use as a datalink.
•
Inserts the General Purpose Communication Channel (GC) byte from the TDPR block when
the TNETOP bit in the S/UNI-JET Data Link and FERF Control Register is logic zero;
otherwise, the byte is set to all ones. The GC byte can be overwritten by using the TOH[x]
and TOHINS[x] input pins.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
70
PMC [ PMC-SIERRA, INC ]
