S/UNI®-JET Data Sheet
Released
Figure 7 HCS Verification State Diagram
ATM DELINEATION
SYNC STATE
ALPHA
consecutive
incorrect HCS's
(To HUNT state)
No Errors
Detected
(Pass Cell)
Apparent Multi-Bit Error
(Drop Cell)
CORRECTION
MODE
Single Bit Error
(Correct error
and pass cell)
Drop Cell
DETECTION
MODE
DELTA
No Errors Detected in M
(M = 1, 2, 4, or 8) consecutive cells
(Pass Last Cell)
consecutive
correct HCS's
(From PRESYNC
state)
In normal operation, the HCS verification state machine remains in the 'Correction' state.
Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit
errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit
error or a multi-bit error, the state machine transitions to the 'Detection' state.
A programmable hysteresis is provided when dropping cells based on HCS errors. When a cell
with an HCS error is detected, the RXCP-50 can be programmed to continue to discard cells until
m (where m = 1, 2, 4, 8) cells are received with a correct HCS. The mth cell is not discarded (see
Figure 7). Note: The dropping of cells due to HCS errors only occurs while the ATMF is in the
SYNC state.
Cell delineation can optionally be disabled, allowing the RXCP-50 to pass all data bytes it
receives.
10.11 RXFF Receive FIFO
The Receive FIFO (RXFF) provides FIFO management and the S/UNI-JET receive cell interface.
The receive FIFO contains four cells. The FIFO provides the cell rate decoupling function
between the transmission system physical layer and the ATM layer.
The general management functions of the RXFF are:
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
68
PMC [ PMC-SIERRA, INC ]
